XSG Application Manual

Overview

XSG (eXtended Sound Generator) is a sound generation device. It is strongly inspired by classic sound chips, such as General Instrument's AY-3-8910 (for the purposes of this reference, we'll call it the PSG), Konami's SCC and Yamaha's OPN family. It features six wave generators with customizable waveforms, two noise generators, two envelope generators and two timers. It also features internal memory for storing waveforms and is capable of stereo sound output.

Features

• 6 sound channels;
• 8 octaves range;
• 2 noise generators;
• 2 envelope generators;
• 2 timers;
• Stereo sound output;
• Customizable tones with 32 byte waveforms;
• 4096 bytes of internal memory for waveform storage;
• Software compatible with the PSG;
• Write-only mode (software selectable) to avoid hardware conflicts.

Description of functions

All functions of XSG are controlled by internal registers. The CPU writes data to XSG internal registers, and XSG generates sound. Sound is generated by the following blocks:

Music generator:

Waveforms having different frequencies are generated for each channel (A, B, C, D, E and F).

Noise generator:

Pseudo-random waveforms having different frequencies are generated for each sound unit (1 for channels A, B and C and 2 for channels D, E and F).

Mixers:

Music and noise output are mixed for the six channels, and further mixed into two stereo channels (left and right). Waveforms can also be inverted for a pseudo-surround effect.

Level control:

Level can be set for each of the six channels. Levels may be controlled by the CPU or by the envelope generators for each sound unit (1 for channels A, B and C and 2 for channels D, E and F).

Envelope generators:

Generates various types of attenuation.

Timers:

Two timers with different resolutions can be useful for music replayers and other applications.

D-A converter:

Sound is output for each of the six channels (A, B, C, D, E and F).

The CPU can read the contents of the internal registers, except when XSG is in write-only mode. This mode is provided to avoid hardware conflicts (for example, if XSG is used to mirror another PSG).

Sound units

XSG is designed to work as two PSGs in tandem. For this reason, there are two noise generators and two envelope generators, one for each sound unit. For maximum compatibility, these units have the exact same features. These sound units are configured from start to work as closely as possible as two PSGs. Thus, each sound channel is set to produce 50% duty-cycle pulse waves and monoaural sound. The equations provided below assume an undivided master clock frequency on the 3.58MHz ballpark, unlike the original PSG and its clones which used half that much.

The register array

Please refer to the register map reference for an overview of the register array. The register array is organized in 3 register banks:

1. Registers R₀₀ to R_0D: used to set parameters for sound unit 1 (sound channels A, B and C);
2. Registers R₁₀ to R_1D: used to set parameters for sound unit 2 (sound channels D, E and F);
3. Registers R₂₄ to R_{27 and RF0 to} R_FE: used to set parameters for features not available in the original PSG.

Unused bits are greyed out. Since they can be used for future features, you should always set them to 0, except when noted otherwise.

Banks 1 and 2 register values usually default to 0 (except when otherwise noted), but for compatibility purposes and best practices, should not be considered as such. You should always initialize these registers by software.

Register bank 1 (channels A, B and C)

Sound unit 1 frequency settings (registers R₀₀ to R₀₅)

Frequencies for each channel are set with the register value TP (Tone Period), which has 12 bits. Since XSG is a 8-bit sound generation device, two registers must be used to set each channel frequencies. The 8 less significant bits are in even-numbered registers and the 4 most significant bits are in odd-numbered registers, according to each sound channel. Thus, R₀₀ and R₀₁ set the frequency for channel A, R₀₂ and R₀₃ for channel B and R₀₄ and R₀₅ for channel C.

The frequency can be calculated by the following equation:

f_T = f_Master / 32TP

f_Master is the master clock frequency. TP is the 12-bit value and f_T is the final tone frequency.

Noise generator 1 setting (register R₀₆)

The noise generator 1 frequency is set with the register value NP (Noise Period), which has 5 bits. The following equation is used to calculate the noise generator 1 frequency:

f_N = f_Master / 32NP

f_Master is the master clock frequency. NP is the 5-bit value and f_N is the final noise frequency.

Sound unit 1 mixer setting (register R₀₇)

The mixer is used to combine music and noise components. The combination is determined by bits B₀ to B₅ of register R₀₇. Sound is output when 0 is written to the register. Thus, when both noise and tone are 0, the output is combined by the mixer. When noise is 0 and tone is 1, only noise is output. When noise is 1 and tone is 0, only the waveform is output. Nothing is output when both bits are 0. Differently from the original PSG, bits B₆ and B₇ are not used. For maximum compatibility with the MSX platform, B₆ always returns 0 when read, while B₇ always returns 1. Thus:

• B₀: Sound channel A tone (0 to set);
• B₁: Sound channel B tone (0 to set);
• B₂: Sound channel C tone (0 to set);
• B₃: Sound channel A noise (0 to set);
• B₄: Sound channel B noise (0 to set);
• B₅: Sound channel C noise (0 to set);
• B₆: always 0;
• B₇: always 1.

Sound unit 1 level control (registers R₀₈ to R_0A)

Each level control register's bit B₄ is the mode select. If its value is 0, then level is controlled by envelope generator 1. If its value is 1, then level is determined by a 4-bit value in bits B₀ to B₃. The channel A level is controlled by register R₀₈, while R₀₉ and R_0A refer to channels B and C, respectively.

Sound level in XSG is logarithmic, just like the PSG, and this behavior is closer to the way human hearing works. Since 15 is the maximum level, and each level step is √2 times louder or quieter than the previous level, this means level 13 is half as loud as level 15, and so on. Conversely, level 10, for example, is twice as loud as level 8, and so on. The only exception to this is when XSG is in linear amplitude mode. In this mode, each level corresponds approximately to 6.7% (1/15) of full volume.

Envelope generator 1 setting (registers R_0B and R_0C)

Envelope repetition frequency is set with the register value EP (Envelope Period), which has 16 bits. Since XSG is a 8-bit sound generation device, two registers must be used to set the envelope generator frequency. The less significant bits are in R_0B and the most significant bits are in R₀₉. This equation can be used to calculate the frequency:

f_E = f_Master / 512EP

f_Master is the master clock frequency. EP is the 16-bit value and f_E is the final envelope frequency. The period of the actual frequency f_EA used for the generated envelope is 1/32 of the envelope repetition period (1/f_E).

Envelope generator 1 shape control (register R_0D)

XSG's envelope generators count the envelope clock f_EA 32 times for each envelope pattern cycle. The envelope level is determined by the 5-bit output of the counter. The shape of this envelope is created by increasing, decreasing, stopping or repeating this counter, and is controlled by register R_0D's bits B₀ to B₃:

• B₀: HLD - hold;
• B₁: ALT - alternate;
• B₂: ATT - attack;
• B₃: CTN - continuous;
• B₄ to B₇: unused.

The following table shows a graphical representation of the envelope generator output,

Envelope Generator Output

B7	B6	B5	B4	B3	B2	B1	B0	Envelope Shape
				CTN	ATT	ALT	HLD
				0	0	x	x
				0	1	x	x
				1	0	0	0
				1	0	0	1
				1	0	1	0
				1	0	1	1
				1	1	0	0
				1	1	0	1
				1	1	1	0
				1	1	1	1

Register bank 2 (channels D, E and F)

Register function and layout for sound unit 2 is exactly the same as for sound unit 1. By adding 10₁₆ to each register number, settings for channels D, E and F instead of channels A, B and C can be changed. Equally, noise generator 2 and envelope generator 2 are set instead of noise generator 1 and envelope generator 1. The only exception to this is when mirror mode is set. In this case, R₁₀ to R_1D will have the same values of R₀₀ to R_0D, and vice versa. You will still be able to change waveform and stereo settings for each channel separately.

Register bank 3 (control set)

The bank 3 registers are used for features new to XSG. For this reason, they all default to 0 and don't need to be initialized by software. This is to ensure XSG can be used for PSG applications with minimal or no modifications.

Timer A (registers R₂₄ and R₂₅)

XSG provides two timers tied to its master clock frequency. Timer A is a high resolution timer (approximately 8.9µs), and it uses 10 bits to set its period (most significant 8 bits are in register R₂₄, and the less significant 2 bits are in register R₂₅. Its frequency is calculated by the following equation:

f_TA = f_Master / 32 * (1024 - P_TA)

f_Master is the master clock frequency. P_TA is the 10 bits period and f_TA is the final timer frequency.

Timer B (register R₂₆)

Timer B is a low resolution timer (approximately 143µs), and it uses 8 bits to set its period. Its frequency is calculated by the following equation:

f_TB = f_Master / 512 * (256 - P_TB)

f_Master is the master clock frequency. P_TB is the 8 bits period and f_TB is the final timer frequency.

Timer control (register R₂₇)

This register is used to control the timers, according to the following:

• B₀ and B₁ (Load):
  • 1: The timer is running.
  • 0: The timer is stopped.
• B₂ and B₃ (Enable):
  • 1: The timer, when overflowing, sets its flag in the status register (R_FD).
  • 0: The timer doesn't set its flag when overflowing.
• B₃ and B₄ (Reset):
  • Write 1 to these bits to reset the respective flag in the status register (R_FD). This bit is reset to 0 at the same time. Writing 0 to these bits has no effect.

Waveform select (registers R_F0 to R_F6)

Each one of these 7 registers (one for each sound channel, from A to F, plus another two for fine addressing and data I/O) point to a waveform in the 4096 bytes of internal storage. Since each waveform has 32 bytes, up to 128 waveforms can be stored internally. The internal address storage is calculated by the following equation:

A_W = 32P_W + O_W

A_W is the internal address. P_W is the value of the pointer, and O_W is the offset. R_F6 works differently, in that it doesn't select a waveform for a specific sound channel. Instead, it selects a waveform that will be written to or read from R_F8.

Waveform offset (register R_F7)

When needed, you can point to a specific byte inside a given waveform. This register is automatically reset when writing to register R_F6.

Waveform data (register R_F8)

XSG has an internal 12-bit address pointer. It points to an internal 4096 byte storage area, and its 7 most significant bits map to register R_F6, while its 5 less significant bits map to register R_F7. When setting the value of R_F6, this value is shifted to the most significant 7 bits of the address pointer (effectively multiplying it for 32). The less significant bits are then reset to 0. When writing or reading a value to or from the waveform data register (R_F8), the address pointer automatically increments. When it reaches 0FFF₁₆, it wraps around to 0. This way, data can be written or read sequentially to or from R_F8, simplifying waveform loading routines. Also, waveform data is 8-bit, unsigned.

In order to achieve compatibility with the PSG, after reset the first 16 bytes of the internal waveform storage area will be filled with FF₁₆, and the following bytes will be at 0, representing a 50% duty-cycle pulse wave in all 6 channels.

Stereo mixer (registers R_FA and R_FB)

The stereo mixer is used to determine whether a given sound channel will output sound to the left, right or center. R_FA controls stereo output for sound channels A, B and C, while R_FB controls stereo output for channels D, E and F. Otherwise, they work the same way. Each control bit is used by each channel, as follows:

• B₀: Sound channel A left output (0 to set);
• B₁: Sound channel B left output (0 to set);
• B₂: Sound channel C left output (0 to set);
• B₃: Sound channel A right output (0 to set);
• B₄: Sound channel B right output (0 to set);
• B₅: Sound channel C right output (0 to set);
• B₆ and B₇: unused.

For compatibility and consistence purposes (similarity to registers R₀₇ and R₁₇), each bit is activated with the value 0. Since the default register value is also 0, sound is output by each channel to both left and right, resulting in monoaural sound by default. If left for a given sound channel is 0 and right is 1, sound will be produced only on the left side. Conversely, if left is 1 and right is 0, sound will be produced only on the right side. A special case happens when both bits are set to 1: instead of muting the output, the waveform is inverted in the right output, giving a pseudo surround effect. These registers values are ignored when XSG is set to monoaural mode.

Operation mode (register R_FC)

This register is used to set XSG operation modes:

• B₀: Write-only mode (WO);
• B₁: Mirror mode (MR);
• B₂: Monoaural mode (MA);
• B₃: Linear amplitude mode (LA);
• B₄ to B₇: reserved.

These bits are all activated by the value 1. Since 0 is the register's default value, they are unset by default.

When XSG is in write-only mode, registers can't be read. With this, it becomes possible to set XSG to the same I/O ports of an existing PSG. This may be useful if you want to use XSG's new features with software written for PSG.

When XSG is in mirror mode, any value written to any Bank 1 register will also be written to the corresponding Bank 2 register. Conversely, any value written to any Bank 2 register will also be written to the corresponding Bank 1 register. This may be useful to play the same notes with different waveforms in full stereo, for example. Effectively, polyphony is sacrificed for the sake of having more complex sounds.

When XSG is in monoaural mode, stereo mixer settings are completely ignored. This may be useful if XSG is connected to a monoaural sound amplifier.

When XSG is in linear amplitude mode, level control is linear instead of logarithmic. This is closer to the way Konami SCC works and may be useful if you want to mimic that particular chip's dynamic response.

Status (register R_FD)

This register is used to check for the timer flags. When the timers are running and they overflow, their respective flags are set to 1 in this register. These flags can't be reset to 0 by writing directly to this register; use the timer control register (R₂₇) instead, when needed.

Test (register R_FE)

This register is used for device detection and to check the device id and revision.

Test (register R_3F)

This register is used to test for the presence of XSG and obtain its revision version.